Avago Technologies LSI53C876E - Manual (Page 10)

x Contents
Index
Customer Feedback
Figures
1.1 Typical LSI53C876 System Application 1-2
1.2 Typical LSI53C876 Board Application 1-3
2.1 LSI53C876 Block Diagram 2-2
2.2 Parity Checking/Generation 2-20
2.3 DMA FIFO Sections 2-20
2.4 LSI53C876 Host Interface SCSI Data Paths 2-24
2.5 LSI53C876 Differential Wiring Diagram 2-27
2.6 Regulated Termination 2-29
2.7 Determining the Synchronous Transfer Rate 2-32
2.8 Block Move and Chained Block Move Instructions 2-40
3.1 LSI53C876 208-Pin PQFP Diagram 3-2
3.2 LSI53C876 256-Ball BGA Diagram (Top View) 3-3
3.3 LSI53C876 Functional Signal Grouping 3-4
5.1 SCRIPTS Overview 5-5
5.2 Block Move Instruction Register 5-8
5.3 I/O Instruction Register 5-16
5.4 Read/Write Instruction Register 5-23
5.5 Transfer Control Instruction 5-29
5.6 Memory Move Instruction 5-37
5.7 Load and Store Instruction Format 5-41
6.1 Rise and Fall Time Test Conditions 6-10
6.2 SCSI Input Filtering 6-10
6.3 Hysteresis of SCSI Receivers 6-10
6.4 Input Current as a Function of Input Voltage 6-11
6.5 Output Current as a Function of Output Voltage 6-11
6.6 Clock Timing 6-12
6.7 Reset Input 6-13
6.8 Interrupt Output 6-14
6.9 Configuration Register Read 6-17
6.10 Configuration Register Write 6-18
6.11 Target Read (Not From External Memory) 6-19