Avago Technologies LSI53C876E - Manual (Page 183)

SCSI Registers 4-89
SCSI operation. Both the SCLK Doubler Enable DBLEN
and SCLK Double Select DBLSEL bits must be set in
either SCSI function to get the internal 80 MHz SCSI
clock.
DBLSEL SCLK Doubler Select 2
This bit, when set, selects the output of the internal clock
doubler for use as the internal SCSI clock. When reset,
this bit selects the clock presented on SCLK for use as
the internal SCSI clock.
R Reserved [1:0]
The LSI53C876 SCSI clock doubler doubles a 40 MHz
SCSI clock, increasing the frequency to 80 MHz. Follow
these steps to use the clock doubler.
1. Set the SCLK Doubler Enable bit ( SCSI Test One
(STEST1) , bit 3).
2. Wait 20
µ
s.
3. Halt the SCSI clock by setting the Halt SCSI Clock bit
( SCSI Test Three (STEST3) , bit 5).
4. Set the clock conversion factor using the SCF and
CCF fields in the SCSI Control Three (SCNTL3)
register.
5. Set the SCLK Doubler Select bit ( SCSI Test One
(STEST1) , bit 2).
6. Clear the Halt SCSI clock bit.