Avago Technologies LSI53C876E - Manual (Page 95)

LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller 4-1
Chapter 4
Registers
This chapter describes all LSI53C876 registers and is divided into the
following sections:
•
Section 4.1, “PCI Configuration Registers”
•
Section 4.2, “SCSI Registers”
4.1 PCI Configuration Registers
The PCI Configuration registers are accessed by performing a
configuration read/write to the device with its IDSEL pin asserted and the
appropriate value in AD[10:8] during the address phase of the
transaction. SCSI Function A is identified by a binary value of 000b, and
SCSI Function B by a value of 001b. Each SCSI channel contains the
same register set with identical default values, except the
Interrupt Pin
register.
Table 4.1 shows the PCI configuration registers implemented by the
LSI53C876.
All PCI-compliant devices, such as the LSI53C876, must support the
Vendor ID , Device ID , Command , and Status registers. Support of other
PCI-compliant registers is optional. In the LSI53C876, registers that are
not supported are not writable and return all zeros when read. Only those
registers and bits that are currently supported by the LSI53C876 are
described in this chapter.