Interrupt status (istat), Interrupt status, Istat) – Avago Technologies LSI53C876E User Manual
Page 144: Register: 0x14
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Registers
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
Register: 0x14
Interrupt Status (ISTAT)
Read/Write
This is the only register that is accessible by the host CPU while a
LSI53C876 SCSI function is executing SCRIPTS (without interfering in
the operation of the function). It polls for interrupts if hardware interrupts
are disabled. Read this register after servicing an interrupt to check for
stacked interrupts. For more information on interrupt handling refer to
Chapter 2, “Functional Description.”
ABRT
Abort Operation
7
Setting this bit aborts the current operation under
execution by the LSI53C876 SCSI function. If this bit is
set and an interrupt is received, clear this bit before
reading the
register to prevent
further aborted interrupts from being generated. The
sequence to abort any operation is:
1. Set this bit.
2. Wait for an interrupt.
3. Read the
register.
4. If the SCSI Interrupt Pending bit is set, then read the
SCSI Interrupt Status Zero (SIST0)
or
register to determine the cause of
the SCSI Interrupt and go back to Step 2.
5. If the SCSI Interrupt Pending bit is clear, and the DMA
Interrupt Pending bit is set, then write 0x00 value to
this register.
6. Read the
register to verify the
aborted interrupt and to see if any other interrupting
conditions have occurred.
7
6
5
4
3
2
1
0
ABRT
SRST
SIGP
SEM
CON
INTF
SIP
DIP
0
0
0
0
0
0
0
0