Avago Technologies LSI53C876E User Manual
Page 225
Memory Move Instructions
5-35
•
Both the source and destination addresses must start with the same
address alignment A[1:0]. If source and destination are not aligned,
then an illegal instruction interrupt occurs. For the PCI
register setting to take effect, the source and destination must
be the same distance from a cache line boundary.
•
Indirect addresses are not allowed. A burst of data is fetched from
the source address, put into the DMA FIFO and then written out to
the destination address. The move continues until the byte count
decrements to zero, then another SCRIPTS is fetched from system
memory.
The
DMA SCRIPTS Pointer Save (DSPS)
and
registers are additional holding registers used during the Memory
Move. However, the contents of the
register are preserved.
IT[2:0]
Instruction Type – Memory Move
[31:39]
R
Reserved
[28:25]
These bits are reserved and must be zero. If any of these
bits are set, an illegal instruction interrupt occurs.
NF
No Flush
24
When this bit is set, the LSI53C876 performs a Memory
Move without flushing the prefetch unit. When this bit is
cleared, the Memory Move instruction automatically
flushes the prefetch unit. Use the No Flush option if the
source and destination are not within four instructions of
the current Memory Move instruction.
Note:
This bit has no effect unless the Prefetch Enable bit in the
register is set. For information on
SCRIPTS instruction prefetching, see
TC[23:0]
Transfer Count
[23:0]
The number of bytes to transfer is stored in the lower
24 bits of the first instruction word.