11 dual address cycles (dacs) command, 12 memory read line command – Avago Technologies LSI53C876E User Manual
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PCI Functional Description
2-7
bus when the Read Multiple Mode is enabled. This mode is enabled by
setting bit 2 (ERMP) of the
register. If cache mode
is enabled, a Read Multiple command is issued on all read cycles, except
opcode fetches, when the following conditions are met:
•
The CLSE bit (Cache Line Size Enable, bit 7,
register) and the ERMP bit (Enable Read Multiple, bit 2,
register) are set.
•
The
register for each function contains a legal burst
size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the
burst size.
•
The number of bytes to transfer at the time a cache boundary is
reached is at least twice the full cache line size.
•
The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to read is a multiple of the cache line size specified in Revision 2.1 of
the PCI specification. The logic selects the largest multiple of the cache
line size based on the amount of data to transfer, with the maximum
allowable burst size determined from the
burst size
bits, and the
, bit 2.
2.1.2.11 Dual Address Cycles (DACs) Command
The LSI53C876 does not respond to this command as a slave, and it
never generates this command as a master.
2.1.2.12 Memory Read Line Command
This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data transfers
where the memory system and the requesting master might gain some
performance advantage by reading up to a cache line boundary rather
than a single memory cycle. The Read Line function in the previous
LSI53C8XX chips is modified in the LSI53C876 to reflect the PCI
register specifications. The functionality of the Enable Read