Avago Technologies LSI53C876E - Manual (Page 200)

5-10 SCSI SCRIPTS Instruction Set
– If the SCSI Group Code is either Group 0, Group 1,
Group 2, or Group 5, then the LSI53C876
overwrites the
DMA Byte Counter (DBC) register
with the length of the Command Descriptor Block:
6, 10, or 12 bytes.
– If the Vendor Unique Enhancement 0 (VUE0) bit
( SCSI Control Two (SCNTL2) , bit 1) is set and the
SCSI group code is a vendor unique code, the
LSI53C876 overwrites the
DMA Byte Counter
(DBC) register with the length of the Command
Descriptor Block: 6, 10, or 12 bytes. If the VUE0 bit
is set, the LSI53C876 receives the number of bytes
in the byte count regardless of the group code.
– If any other Group Code is received, the DMA Byte
Counter (DBC) register is not modified and the
LSI53C876 requests the number of bytes specified
in the
DMA Byte Counter (DBC) register. If the DBC
register contains 0x000000, an illegal instruction
interrupt is generated.
4. The LSI53C876 transfers the number of bytes
specified in the DMA Byte Counter (DBC) register
starting at the address specified in the DMA Next
Address (DNAD) register. If the Opcode bit is set and
a data transfer ends on an odd byte boundary, the
LSI53C876 stores the last byte in the
SCSI Wide
Residue (SWIDE) register during a receive operation.
This byte is combined with the first byte from the
subsequent transfer so that a wide transfer can be
completed.
5. If the SATN/ signal is asserted by the Initiator or a
parity error occurred during the transfer, the transfer
can optionally be halted and an interrupt generated.
The Disable Halt on Parity Error or ATN bit in the
SCSI Control One (SCNTL1) register controls
whether the LSI53C825A halts on these conditions
immediately, or waits until completion of the current
Move.