Avago Technologies LSI53C876E - Manual (Page 67)

Serial EEPROM Interface 2-45
The LSI53C876 allows the system to determine the size of the available
external memory using the
Expansion ROM Base Address register in
PCI configuration space. For more information on how this works, refer
to the PCI specification or the
Expansion ROM Base Address register
description in Chapter 4, “Registers.”
MAD[0] is the slow ROM pin. When pulled down, it enables two extra
clock cycles of data access time to allow use of slower memory devices.
The external memory interface also supports updates to Flash memory.
2.4 Serial EEPROM Interface
The LSI53C876 implements an interface that allows attachment of a
serial EEPROM device to the GPIO0 and GPIO1 pins for each SCSI
function. There are several modes of operation. These relate to the serial
EEPROM and the
Subsystem ID register and Subsystem Vendor ID
register for each SCSI function. These modes are programmable through
the MAD6 and MAD7 pins which are sampled at power-up or hard reset.
2.4.1 Mode A Operation
No pull-down on MAD6, no pull-down on MAD7. In this mode, GPIO0 is
the serial data signal (SDA) and GPIO1 is the serial clock signal (SCL).
Certain data in the serial EEPROM is automatically loaded into chip
registers at power-up or hard reset.
The format of the serial EEPROM data is defined in Table 2.7 . If the
EEPROM is not present, or the checksum fails, the Subsystem ID and
Subsystem Vendor ID registers read back all zeros. At power-up or hard
reset, only five bytes are loaded into the chip from locations 0x00 through
0x04.
The Subsystem ID and Subsystem Vendor ID registers are read only, in
accordance with the PCI specification, with a default value of all zeros.