Avago Technologies LSI53C876E - Manual (Page 203)

I/O Instruction 5-13
transferred. In addition, the DMA Next Address (DNAD)
register is incremented by the number of bytes
transferred. This process is repeated until the
DMA Byte
Counter (DBC) register is decremented to zero. At this
time, the LSI53C876 fetches the next instruction.
If bit 28 is set, indicating table indirect addressing, this
field is not used. The byte count is instead fetched from
a table pointed to by the
Data Structure Address (DSA)
register.
5.3.2 Second Dword
Start Address [31:0]
This 32-bit field specifies the starting address of the data
to move to/from memory. This field is copied to the
DMA
Next Address (DNAD) register. When the LSI53C876
transfers data to or from memory, the DNAD register is
incremented by the number of bytes transferred.
When bit 29 is set, indicating indirect addressing, this
address is a pointer to an address in memory that points
to the data location. When bit 28 is set, indicating table
indirect addressing, the value in this field is an offset into
a table pointed to by the
Data Structure Address (DSA) .
The table entry contains byte count and address
information.
5.4 I/O Instruction
5.4.1 First Dword
IT[1:0] Instruction Type - I/O Instruction [31:30]
OPC[2:0] OpCode [29:27]
The following OpCode bits have different meanings,
depending on whether the LSI53C876 is operating in
initiator or target mode. OpCode selections 101–111 are
considered Read/Write instructions, and are described in
Section 5.5, “Read/Write Instructions.”