Avago Technologies LSI53C876E - Manual (Page 85)

SCSI Bus Interface Signals 3-13
3.2 SCSI Bus Interface Signals
The SCSI Bus Interface signals section contains tables describing the
signals for the following signal groups:
SCSI Bus Interface Signal and
SCSI Bus Interface .
3.2.1 SCSI Bus Interface Signal
Table 3.9 describes the SCSI Bus Interface signal.
Table 3.9 SCSI Bus Interface Signal
Name Pin No. Type Strength Description
SCLK 65, W6 I N/A SCSI Clock is used to derive all
SCSI-related timings. The speed of this clock
is determined by the application requirements.
In some applications, SCLK may be sourced
internally from the PCI bus clock (CLK). If
SCLK is internally sourced, tie the SCLK pin
LOW. For Ultra SCSI operations, the clock
supplied to SCLK must be at 40 MHz. The
frequency is doubled to create the 80 MHz
clock required by both SCSI functions.