Avago Technologies LSI53C876E - Manual (Page 11)

Contents xi
6.12 Target Write (Not From External Memory) 6-20
6.13 Target Read, from External Memory 6-22
6.14 Target Write, from External Memory 6-26
6.15 Opcode Fetch, Nonburst 6-29
6.16 Opcode Fetch, Burst 6-31
6.17 Back-to-Back Read 6-33
6.18 Back-to-Back Write 6-35
6.19 Burst Read 6-38
6.20 Burst Write 6-42
6.21 Read Cycle, Normal/Fast Memory (
≥
128 Kbytes),
Single Byte Access 6-44
6.22 Write Cycle, Normal/Fast Memory (
≥
128 Kbytes),
Single Byte Access 6-45
6.23 Read Cycle, Normal/Fast Memory (
≥
128 Kbyte),
Multiple Byte Access 6-46
6.24 Write Cycle, Normal/Fast Memory (
≥
128 Kbyte),
Multiple Byte Access 6-48
6.25 Read Cycle, Slow Memory (
≥
128 Kbytes) 6-50
6.26 Write Cycle, Slow Memory (
≥
128 Kbytes) 6-51
6.28 Read Cycle, 16 Kbytes ROM 6-52
6.27 Read Cycle, 16 Kbytes ROM 6-52
6.29 Write Cycle, 16 Kbytes ROM 6-53
6.30 Initiator Asynchronous Send 6-55
6.31 Initiator Asynchronous Receive 6-56
6.32 Target Asynchronous Send 6-57
6.33 Target Asynchronous Receive 6-57
6.34 Initiator and Target Synchronous Transfers 6-58
6.35 256-pin PBGA (GU) Mechanical Drawing 6-61
6.36 208-pin PQFP (P9) Mechanical Drawing (Sheet 1 of 2) 6-62
B.1 64 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 256 Kbyte Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables
2.1 PCI Bus Commands and Encoding Types 2-4
2.2 Bits Used for Parity Control and Generation 2-18
2.3 SCSI Parity Control 2-19