Avago Technologies LSI53C876E - Manual (Page 311)

Index IX-7
register bits (Cont.)
source I/O-memory enable 4-67
SREQ/ status 4-41
SSEL/ status 4-41
start DMA operation 4-71
start SCSI transfer 4-27
start sequence 4-23
synchronous clock conversion factor 4-31
target mode 4-24
timer test mode 4-93
TolerANT enable 4-92
Ultra SCSI enable 4-31
unexpected disconnect 4-74
,
4-78
wide SCSI receive 4-30
wide SCSI send 4-29
won arbitration 4-45
write and invalidate enable 4-57
registers 2-33
reliability 1-7
REQ/ 3-9
REQ/ - GNT/ 1-1
,
2-3
request 3-9
reselected bit 4-74
,
4-77
reserved command 2-5
reset 3-6
reset SCSI offset bit 4-90
RESPID0 register 4-86
RESPID1 register 4-86
response ID one register 4-86
response ID zero register 4-86
revision level bits 4-56
ROM 3-18
ROM base address register 2-44
ROM interface 2-43
ROM pin 2-45
ROM/flash interface signals 3-18
RST/ 3-6
RSTDIR 3-16
,
3-17
S
SACK 2-38
SACK/ 3-14
,
3-15
SACK/ status bit 4-41
SATN/ 3-14
,
3-15
SATN/ active 4-77
SATN/ active bit 4-77
SATN/ status bit 4-41
SBCL register 4-41
SBDL register 4-95
SBSY status bit 4-41
SBSY/ 3-14
,
3-15
SC_D/ 3-14
,
3-15
SC_D/ status bit 4-41
scatter/gather 1-6
SCF[2:0] 2-30
SCID register 4-32
SCLK 3-13
SCNTL0 register 4-22
SCNTL1 register 4-25
SCNTL2 register 4-28
SCNTL3 register 4-31
SCRATCHA register 4-66
SCRATCHB register 4-96
SCRIPTS instruction 2-41
SCRIPTS interrupt instruction received bit 4-43
SCRIPTS processor 2-13
instruction prefetching 2-14
internal RAM for instruction storage 2-14
performance 2-13
SCRIPTS RAM 2-4
,
2-14
SCSI
differential mode 2-24
termination 2-28
SCSI ATN condition - target mode 4-73
SCSI ATN condition bit 4-73
SCSI bus control lines register 4-41
SCSI bus data lines register 4-95
SCSI bus interface 2-24
SCSI C_D/ signal bit 4-47
SCSI chip ID register 4-32
SCSI clock 3-13
,
3-16
,
3-17
SCSI control 3-14
,
3-15
,
3-16
,
3-17
SCSI control enable bit 4-90
SCSI control one register 4-25
SCSI control three register 4-31
SCSI control two register 4-28
SCSI control zero register 4-22
SCSI controller 2-13
SCSI core 1-3
SCSI data high impedance bit 4-59
SCSI destination ID register 4-36
SCSI disconnect unexpected bit 4-28
SCSI FIFO test read bit 4-92
SCSI FIFO test write bit 4-94
SCSI first byte received register 4-38
SCSI gross error bit 4-74
,
4-77
SCSI high impedance mode bit 4-91
SCSI I_O/ signal bit 4-47
SCSI input data latch register 4-94
SCSI instructions
block move 5-6
I/O 5-13
load/store 5-38
memory move 5-34
read/write 5-22
transfer control 5-27
SCSI interrupt enable one register 4-75
SCSI interrupt enable zero register 4-73
SCSI interrupt pending bit 4-52
SCSI interrupt status one register 4-79
SCSI interrupt status zero register 4-76
SCSI interrupts 2-38
SCSI longitudinal parity register 4-80
SCSI loopback mode bit 4-90
SCSI low level mode bit 4-91
SCSI MSG/ signal bit 4-47
SCSI output control latch register 4-39
SCSI output data latch register 4-95
SCSI parity error bit 4-75
SCSI performance 1-5
SCSI phase mismatch bit 4-73
SCSI reset condition bit 4-75
SCSI RST/ received bit 4-78
SCSI RST/ signal bit 4-45
SCSI SCRIPTS 1-3
SCSI SCRIPTS operation 5-2
sample instruction 5-3
SCSI SDP0/ parity signal bit 4-46
SCSI SDP1 signal bit 4-49
SCSI selected as ID bits 4-87
SCSI selector ID register 4-40