1 pci and external memory interface timings, Pci and external memory interface timings – Avago Technologies LSI53C876E User Manual

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AC Characteristics

6-15

6.4.1 PCI and External Memory Interface Timings

Figure 6.9

through

Figure 6.29

represent signal activity when the

LSI53C876 accesses the PCI bus. This section includes timing diagrams
for access to three groups of external memory configurations. The first
group applies to systems with memory size of 128 Kbytes and above;
one byte read or write cycle, and fast or normal ROMs. The second
group applies to systems with memory size of 128 Kbytes and above,
one byte read or write cycles, and slow ROMs. The third group applies
to systems with memory size of 64 Kbytes or less, one byte read or write
cycles, and normal or fast ROM.

Note:

Multiple byte access to the external memory bus increases
the read or write cycle by 11 clocks for each additional byte.
For your convenience, we have created one table with all
the symbols and parameters for all the timing diagrams as
well as included a table for each timing diagram.

Timing diagrams included in this section:

•

Configuration Register Read

•

Configuration Register Write

•

Target Read (Not From External Memory)

•

Target Write (Not From External Memory)

•

Target Read, from External Memory

•