Avago Technologies LSI53C876E - Manual (Page 119)

SCSI Registers 4-25
When this bit is set, the chip is a target device by default.
When this bit is cleared, the LSI53C876 SCSI function is
an initiator device by default.
Note: Writing this bit while not connected may cause the loss of
a selection or reselection due to the changing of target or
initiator modes.
Register: 0x01
SCSI Control One (SCNTL1)
Read/Write
EXC Extra Clock Cycle of Data Setup 7
When this bit is set, an extra clock period of data setup
is added to each SCSI send data transfer. The extra data
setup time can provide additional system design margin,
though it affects the SCSI transfer rates. Clearing this bit
disables the extra clock cycle of data setup time. Setting
this bit only affects SCSI send operations.
ADB Assert SCSI Data Bus 6
When this bit is set, the LSI53C876 SCSI function drives
the contents of the
SCSI Output Data Latch (SODL)
register onto the SCSI data bus. When the LSI53C876
SCSI function is an initiator, the SCSI I/O signal must be
inactive to assert the SODL contents onto the SCSI bus.
When the LSI53C876 SCSI function is a target, the SCSI
I/O signal must be active to assert the SODL contents
onto the SCSI bus. The contents of the SODL register
can be asserted at any time, even before the LSI53C876
SCSI function is connected to the SCSI bus. Clear this bit
when executing SCSI SCRIPTS. It is normally used only
for diagnostics testing or operation in low level mode.
DHP Disable Halt on Parity Error or ATN (Target Only) 5
The DHP bit is only defined for target mode. When this
bit is cleared, the LSI53C876 SCSI function halts the
SCSI data transfer when a parity error is detected or
when the SATN/ signal is asserted. If SATN/ or a parity
error is received in the middle of a data transfer, the
7 6 5 4 3 2 1 0
EXC ADB DHP CON RST AESP IARB SST
0 0 0 0 0 0 0 0