Chip test six, Ctest6), Register: 0x23 – Avago Technologies LSI53C876E User Manual
Page 156
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Registers
BL2
Burst Length, Bit 2
2
This bit works with bits 6 and 7 in the
register to determine the burst length. For
complete definitions of this field, refer to the descriptions
of DMODE bits 6 and 7. This bit is disabled if an 88-byte
FIFO is selected by clearing the DMA FIFO size bit.
BO[9:8]
DMA FIFO Byte Offset Counter, Bits [9:8]
[1:0]
These are the upper two bits of the DFBOC. Refer to the
DFBOC register description for encodings of the BO[9:0]
bits.
Register: 0x23
Chip Test Six (CTEST6)
Read/Write
DF
DMA FIFO
[7:0]
Writing to this register writes data to the appropriate byte
lane of the DMA FIFO as determined by the FBL bits in
the
register. Reading this
register unloads data from the appropriate byte lane of
the DMA FIFO as determined by the FBL bits in the
CTEST4 register. Data written to the FIFO is loaded into
the top of the FIFO. Data read out of the FIFO is taken
from the bottom. To prevent DMA data from being
corrupted, this register should not be accessed before
starting or restarting SCRIPTS operation. Write this
register only when testing the DMA FIFO using the
register. Writing to this register while
the test mode is not enabled produces unexpected
results.
7
0
DF
0
0
0
0
0
0
0
0