Avago Technologies LSI53C876E - Manual (Page 305)

LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller IX-1
Index
Symbols
(AD[31:0]) 3-7
(BARO[31:0]) 4-10
(BART[31:0]) 4-10
(BARZ[31:0]) 4-9
(BSE[7:0]) 4-19
(CCF[2:0]) 2-30
(CID[7:0]) 4-16
(CLS[7:0]) 4-7
(CP[7:0]) 4-14
(DATA[7:0]) 4-20
(ERBA[31:0]) 4-13
(HT[7:0]) 4-8
(IL[7:0]) 4-14
(IP[7:0]) 4-15
(LT[7:0]) 4-8
(MAD[7:0]) 3-18
(MG[7:0]) 4-15
(ML[7:0]) 4-16
(NIP[7:0]) 4-17
(SID[15:0]) 4-12
Numerics
3.3/5 V PCI interface 2-11
,
2-17
3-state 3-5
40 MHz clock doubler 2-31
A
abort operation bit 4-50
aborted bit 4-43
,
4-69
AC characteristics 6-12
PCI and external memory interface timing 6-15
SCSI interface timing 6-55
active negation
see TolerANT technology
active termination 2-28
ADDER register 4-72
adder sum output register 4-72
address/data bus 2-3
address/data signals 3-7
alignment 2-11
always wide SCSI bit 4-91
arbitration
arbitration in progress bit 4-45
arbitration mode bits 4-22
full arbitration 4-22
immediate arbitration bit 4-26
lost arbitration bit 4-45
simple arbitration 4-22
won arbitration bit 4-45
arbitration in progress bit 4-45
arbitration mode bits 4-22
arbitration pins 3-9
arbitration priority encoder test bit 4-87
ASPI 1-3
assert even SCSI parity bit 4-26
assert SATN/ on parity error bit 4-24
assert SCSI ACK/ signal bit 4-39
assert SCSI ATN/ signal bit 4-39
assert SCSI BSY/ signal bit 4-39
assert SCSI C_D/ signal bit 4-39
assert SCSI data bus bit 4-25
assert SCSI I_O signal bit 4-39
assert SCSI MSG/ signal bit 4-39
assert SCSI REQ/ signal bit 4-39
assert SCSI RST/ signal bit 4-26
assert SCSI SEL/ signal bit 4-39
asynchronous SCSI receive 2-22
asynchronous SCSI send 2-21
autoconfiguration disable 3-21
B
base address register
one (BARO[31:0]) 4-10
two (BART[31:0]) 4-10
zero - I/O (BARZ[31:0]) 4-9
base address register one 2-4
bidirectional 3-5
big and little endian support 2-17
BIOS 2-3
BIOS ROM 1-1
block move instructions 5-6
bridge support extensions (BSE[7:0]) 4-19
BSYDIR 3-16
burst disable bit 4-59
burst length bits 4-62
,
4-66
burst opcode fetch enable bit 4-68
burst size selection 2-7
bus command and byte enables 3-7
bus fault bit 4-42
,
4-69
byte empty in DMA FIFO bit 4-54
byte full in DMA FIFO bit 4-54
byte offset counter bits 4-58
,
4-62
C
C_BE/[3:0] 2-3
,
3-7
cache line size
(CLS[7:0]) 4-7