Avago Technologies LSI53C876E - Manual (Page 108)

4-14 Registers
Register: 0x34
Capabilities Pointer
Read Only
CP Capabilities Pointer [7:0]
This register provides an offset into the function’s PCI
Configuration Space for the location of the first item in the
capabilities linked list. Only the LSI53C876E sets this
register to 0x40.
Register: 0x3C
Interrupt Line
Read/Write
IL Interrupt Line [7:0]
This register can communicate interrupt line routing
information. POST software writes the routing information
into this register as it configures the system. The value in
this register tells which input of the system interrupt
controller(s) the device’s interrupt pin is connected to.
Values in this register are specified by system
architecture.
7 0
CP
0 1 0 0 0 0 0 0
7 0
IL
0 0 0 0 0 0 0 0