Avago Technologies LSI53C876E - Manual (Page 169)

SCSI Registers 4-75
RST SCSI Reset Condition 1
Setting this bit allows the LSI53C876 to generate an
interrupt when the SRST/ signal has been asserted by
the LSI53C876 or any other SCSI device. This condition
is edge-triggered, so multiple interrupts cannot occur
because of a single SRST/ pulse.
PAR SCSI Parity Error 0
Setting this bit allows the LSI53C876 to generate an
interrupt when the LSI53C876 detects a parity error while
receiving or sending SCSI data. See the Disable Halt on
Parity Error or SATN/ Condition bits in the
SCSI Control
One (SCNTL1) register for more information on when this
condition is actually raised.
Register: 0x41
SCSI Interrupt Enable One (SIEN1)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status One
(SIST1) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts, refer to Chapter 2, “Functional
Description.”
R Reserved [7:4]
WIE Wakeup Interrupt Enable 3
Setting this bit allows the LSI53C876E to enable /IRQ on
SCSI reset.
STO Selection or Reselection Time-out 2
Setting this bit allows the LSI53C876 to generate an
interrupt when a selection or reselection time-out occurs.
See the description of the
SCSI Timer Zero (STIME0)
register bits [3:0] for more information on the time-out
periods.
7 4 3 2 1 0
R WIE STO GEN HTH
x x x x 0 0 0 0