Altera Arria V Hard IP for PCI Express - Manual (Page 98)

6–24 Chapter 6: IP Core Architecture
Single DWord Completer Endpoint
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
f For more information about legal combinations of byte enables, refer to Chapter 3,
Avalon Memory-Mapped Interfaces in the
Avalon Interface Specifications.
TX Block
The TX block sends completion information to the Avalon-MM Hard IP for PCI
Express which sends this information to the root complex. The TX completion block
generates a completion packet with Completer Abort (CA) status and no completion
data for unsupported requests. The TX completion block also supports the
zero-length read (flush) command.
Interrupt Handler Block
The interrupt handler implements both INTX and MSI interrupts. The msi_enable bit
in the configuration register specifies the interrupt type. The msi_enable_bit is part
of MSI message control portion in MSI Capability structure. It is bit[16] of 0x050 in the
Configuration Space registers. If the
msi_enable bit is on, an MSI request is sent to the
Arria V Hard IP for PCI Express when received, otherwise INTX is signaled. The
interrupt handler block supports a single interrupt source, so that software may
assume the source. You can disable interrupts by leaving the interrupt signal
unconnected in the IRQ column of Qsys. When the MSI registers in the Configuration
Space of the completer only single dword Arria V Hard IP for PCI Express are
updated, there is a delay before this information is propagated to the Bridge module
shown in
Figure 6–13 . You must allow time for the Bridge module to update the MSI
register information. Under normal operation, initialization of the MSI registers
should occur substantially before any interrupt is generated. However, failure to wait
until the update completes may result in any of the following behaviors:
■ Sending a legacy interrupt instead of an MSI interrupt
■ Sending an MSI interrupt instead of a legacy interrupt
■ Loss of an interrupt request