Altera Arria V Hard IP for PCI Express - Manual (Page 131)

Chapter 7: IP Core Interfaces 7–33
Arria V Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Configuration Space Register Access Timing
Figure 7–29 shows typical traffic on the tl_cfg_ctl bus. The tl_cfg_add index
update every eight coreclkout_hip , specifying which Configuration Space register
information is being driven onto tl_cfg_ctl .
[29:25]
Status Register[15:11]
Records the following 5 primary command status errors:
■ Bit 15: detected parity error
■ Bit 14: signaled system error
■ Bit 13: received master abort
■ Bit 12: received target abort
■ Bit 11: signalled target abort
[24]
Secondary Status Register[8]
Master data parity error
[23:6]
Root Status Register[17:0]
Records the following PME status information:
■ Bit 17: PME pending
■ Bit 16: PME status
■ Bits[15:0]: PME request ID[15:0]
[5:1] Secondary Status Register[15:11]
Records the following 5 secondary command status errors:
■ Bit 15: detected parity error
■ Bit 14: received system error
■ Bit 13: received master abort
■ Bit 12: received target abort
■ Bit 11: signalled target abort
[0] Secondary Status Register[8] Master Data Parity Error
Table 7–12. Mapping Between tl_cfg_sts and Configuration Space Registers (Part 2 of 2)
tl_cfg_sts Configuration Space Register Description
Figure 7–29. tl_cfg_ctl Timing
coreclkout_hip
tl_cfg_add[3:0]
tl_cfg_ctl[31:0]
D E F 0 1 2 3
00000084 00000000 28100000 08000000 00000002