Altera Arria V Hard IP for PCI Express - Manual (Page 89)

Chapter 6: IP Core Architecture 6–15
Avalon-MM Bridge TLPs
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
■ The Avalon-MM byte enables may deassert, but only in the last qword of the burst.
1 To improve PCI Express throughput, Altera recommends using an Avalon-MM burst
master without any byte-enable restrictions.
Avalon-MM-to-PCI Express Upstream Read Requests
The PCI Express Avalon-MM bridge converts read requests from the system
interconnect fabric to PCI Express read requests with 32-bit or 64-bit addresses based
on the address translation configuration, the request address, and the maximum read
size.
The Avalon-MM TX slave interface of a PCI Express Avalon-MM bridge can receive
read requests with burst sizes of up to 512 bytes sent to any address. However, the
bridge limits read requests sent to the PCI Express link to a maximum of 256 bytes.
Additionally, the bridge must prevent each PCI Express read request packet from
crossing a 4 KByte address boundary. Therefore, the bridge may split an Avalon-MM
read request into multiple PCI Express read packets based on the address and the size
of the read request.
For Avalon-MM read requests with a burst count greater than one, all byte enables
must be asserted. There are no restrictions on byte enables for Avalon-MM read
requests with a burst count of one. An invalid Avalon-MM request can adversely
affect system functionality, resulting in a completion with the abort status set. An
example of an invalid request is one with an incorrect address.
PCI Express-to-Avalon-MM Read Completions
The PCI Express Avalon-MM bridge returns read completion packets to the initiating
Avalon-MM master in the issuing order. The bridge supports multiple and
out-of-order completion packets.
PCI Express-to-Avalon-MM Downstream Write Requests
The PCI Express Avalon-MM bridge receives PCI Express write requests. It converts
them to burst write requests before sending them to the interconnect fabric. For
Endpoints, the bridge translates the PCI Express address to the Avalon-MM address
space based on the BAR hit information and on address translation table values
configured during the IP core parameterization. For Root Ports, all requests are
forwarded to a single RX Avalon-MM master that drives them to the interconnect
fabric. Malformed write packets are dropped, and therefore do not appear on the
Avalon-MM interface.
For downstream write and read requests, if more than one byte enable is asserted, the
byte lanes must be adjacent. In addition, the byte enables must be aligned to the size
of the read or write request.