Altera Arria V Hard IP for PCI Express - Manual (Page 200)

11–6 Chapter 11: Interrupts
Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 11–5 shows the logic for the entire interrupt generation process.
The PCI Express Avalon-MM bridge selects either MSI or legacy interrupts
automatically based on the standard interrupt controls in the PCI Express
Configuration Space registers. The
Interrupt Disable bit, which is bit 10 of the
Command register (at Configuration Space offset 0x4) can be used to disable legacy
interrupts. The MSI Enable bit, which is bit 0 of the MSI Control Status register in the
MSI capability register (bit 16 at configuration space offset 0x50), can be used to
enable MSI interrupts.
Only one type of interrupt can be enabled at a time. However, to change the selection
of MSI or legacy interrupts during operation, software must ensure that no interrupt
request is dropped. Therefore, software must first enable the new selection and then
disable the old selection. To set up legacy interrupts, software must first clear the
Interrupt Disable bit and then clear the MSI enable bit. To set up MSI interrupts,
software must first set the MSI enable bit and then set the Interrupt Disable bit.
Figure 11–5. Avalon-MM Interrupt Propagation to the PCI Express Link
SET
CLR
D Q
Q
Interrupt Disable
(Configuration Space Command Register [10])
Avalon-MM-to-PCI-Express
Interrupt Status and Interrupt
Enable Register Bits
A2P_MAILBOX_INT7
A2P_MB_IRQ7
A2P_MAILBOX_INT6
A2P_MB_IRQ6
A2P_MAILBOX_INT5
A2P_MB_IRQ5
A2P_MAILBOX_INT4
A2P_MB_IRQ4
A2P_MAILBOX_INT3
A2P_MB_IRQ3
A2P_MAILBOX_INT2
A2P_MB_IRQ2
A2P_MAILBOX_INT1
A2P_MB_IRQ1
A2P_MAILBOX_INT0
A2P_MB_IRQ0
AV_IRQ_ASSERTED
AVL_IRQ
MSI Enable
(Configuration Space Message Control Register[0])
MSI Request
PCI Express Virtual INTA signalling
(When signal rises ASSERT_INTA Message Sent)
(When signal falls DEASSERT_INTA Message Sent)