Altera Arria V Hard IP for PCI Express - Manual (Page 137)

Chapter 7: IP Core Interfaces 7–39
Arria V Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Table 7–16 describes the signals that comprise the LMI interface.
LMI Read Operation
Figure 7–31 illustrates the read operation.
LMI Write Operation
Figure 7–32 illustrates the LMI write. Only writeable configuration bits are
overwritten by this operation. Read-only bits are not affected. LMI write operations
are not recommended for use during normal operation with the exception of AER
header logging.
Table 7–16. LMI Interface
Signal Width Dir Description
lmi_dout 32 O Data outputs
lmi_rden 1 I Read enable input
lmi_wren 1 I Write enable input
lmi_ack 1 O Write execution done/read data valid
lmi_addr 15 I Address inputs, [1:0] not used
lmi_din 32 I Data inputs
Figure 7–31. LMI Read
Figure 7–32. LMI Write
pld_clk
lmi_rden
lmi_addr[14:0]
lmi_dout[31:0]
lmi_ack
coreclkout
lmi_wren
lmi_din[31:0]
lmi_addr[14:0]
lmi_ack