Altera Arria V Hard IP for PCI Express - Manual (Page 96)

6–22 Chapter 6: IP Core Architecture
Single DWord Completer Endpoint
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
■ Sp[1:0] —the space indication for each entry.
Single DWord Completer Endpoint
The single dword completer Endpoint is intended for applications that use the PCI
Express protocol to perform simple read and write register accesses from a host CPU.
The single dword completer Endpoint is a hard IP implementation available for Qsys
systems, and includes an Avalon-MM interface to the Application Layer. The
Avalon-MM interface connection in this variation is 32 bits wide. This Endpoint is not
pipelined; at any time a single request can be outstanding.
The single dword Endpoint completer supports the following requests:
■ Read and write requests of a single dword (32 bits) from the Root Complex
■ Completion with Completer Abort status generation for other types of non-posted
requests
■ INTX or MSI support with one Avalon-MM interrupt source
Figure 6–12. Avalon-MM-to-PCI Express Address Translation
PCIe Address Q-1 SpQ-1
Space Indication
PCI Express address from Table Entry
becomes High PCI Express address bits
PCI Express Address
High Low
P-1 N N-1 0
Low address bits unchanged
Avalon-MM-to-PCI Express
Address Translation Table
(Q entries by P-N bits wide)
PCIe Address 0 Sp0
PCIe Address 1 Sp1
Avalon-MM Address
High
Slave Base
Address
Low
M-1 31 M N N-1 0
Table updates from
control register port
High Avalon-MM Address
Bits Index table