Altera Arria V Hard IP for PCI Express - Manual (Page 104)

7–6 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
rx_st_valid 1 O valid
Clocks rx_st_data into the Application Layer. Deasserts
within 2 clocks of rx_st_ready deassertion and reasserts
within 2 clocks of rx_st_ready assertion if more data is
available to send. rx_st_valid can be deasserted between the
rx_st_sop and rx_st_eop even if rx_st_ready is asserted.
rx_st_err 1 O error
Indicates that there is an uncorrectable ECC error in the internal
RX buffer. Active when ECC is enabled. ECC is automatically
enabled by the Quartus II assembler. ECC corrects single-bit
errors and detects double-bit errors on a per byte basis.
When an uncorrectable ECC error is detected, rx_st_err is
asserted for at least 1 cycle while rx_st_valid is asserted. If
the error occurs before the end of a TLP payload, the packet
may be terminated early with an
rx_st_eop and with
rx_st_valid deasserted on the cycle after the eop.
Altera recommends resetting the Arria V Hard IP for PCI
Express IP core when an uncorrectable (double-bit) ECC error
is detected.
Component Specific Signals
rx_st_mask 1 I
component
specific
The Application Layer asserts this signal to tell the Hard IP to
stop sending non-posted requests. This signal can be asserted
at any time. This signal does not affect non-posted requests
that have already been transferred from the Transaction Layer
to the application interface. The total number of non-posted
requests that can be transferred to the application after
rx_st_mask is asserted not more than 14 for 64-bit mode.,
and is not more than 26 for 128-bit mode.
Table 7–3. 64- or 128-Bit Avalon-ST RX Datapath (Part 2 of 4)
Signal Width Dir
Avalon-ST
Type
Description