Altera Arria V Hard IP for PCI Express - Manual (Page 84)

6–10 Chapter 6: IP Core Architecture
Protocol Layers
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 6–5 illustrates the Physical Layer architecture.
The Physical Layer is subdivided by the PIPE Interface Specification into two layers
(bracketed horizontally in
Figure 6–5 ):
■ Media Access Controller (MAC) Layer—The MAC layer includes the LTSSM and
the scrambling/descrambling and multilane deskew functions.
■ PHY Layer—The PHY layer includes the 8B/10B encode/decode functions, elastic
buffering, and serialization/deserialization functions.
The Physical Layer integrates both digital and analog elements. Intel designed the
PIPE interface to separate the MAC from the PHY. The Arria V Hard IP for PCI
Express complies with the PIPE interface specification.
The PHYMAC block is divided in four main sub-blocks:
■ MAC Lane—Both the RX and the TX path use this block.
■ On the RX side, the block decodes the Physical Layer Packet and reports to the
LTSSM the type and number of TS1/TS2 ordered sets received.
■ On the TX side, the block multiplexes data from the DLL and the LTSTX
sub-block. It also adds lane specific information, including the lane number
and the force PAD value when the LTSSM disables the lane during
initialization.
Figure 6–5. Physical Layer
Scrambler
8B10B
Encoder
Lane n
Tx+ / Tx-
Scrambler
8B10B
Encoder
Lane 0
Tx+ / Tx-
Descrambler
8B10B
Decoder
Lane n
Rx+ / Rx-
Elastic
Buffer
LTSSM
State Machine
SKIP
Generation
Control & Status
PIPE
Emulation Logic
Link Ser
ial iz
er
Link Ser
ial iz
er
Tx Packets
Rx MAC
Lane
De
vice
T
ransceiv
er (per Lane)
w
ith 2.5 or 5.0 G
b
ps SERDES & PLL
Descrambler
8B10B
Decoder
Lane 0
Rx+ / Rx-
Elastic
Buffer
Rx MAC
Lane
PIPE
Interface
Multilane Desk
e
w
Rx Packets
Transmit
Data Path
Receive
Data Path
MAC Layer PHY layer
To Link To Data Link Layer