Altera Arria V Hard IP for PCI Express - Manual (Page 217)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
15. Transceiver PHY IP Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. You must
compensate for this variation by including the Transceiver Reconfiguration Controller
IP Core in your design. You can instantiate this component using the MegaWizard
Plug-In Manager or Qsys. It is available for Arria V devices and can be found in the
Interfaces/Transceiver PHY
category for the MegaWizard design flow. In Qsys, you
can find the Transceiver Reconfiguration Controller in the Interface
Protocols/Transceiver PHY category. When you instantiate your Transceiver
Reconfiguration Controller IP core the Enable offset cancellation block option is On
by default. This feature is all that is required to ensure that the transceivers operate
within the required ranges, but you can choose to enable other features such as the
Enable analog/PMA reconfiguration block
option if your system requires this.
Initially, the Arria V Hard IP for PCI Express requires a separate reconfiguration
interface for each lane and each TX PLL. It reports this number in the message pane of
its GUI. You must take note of this number so the you can enter it as a parameter in
the Transceiver Reconfiguration Controller.
Figure 15–1 illustrates the messages
reported for a Gen2 ×4 variant. The variant requires five interfaces: one for each lane
and one for the TX PLL.
Figure 15–1. Number of External Reconfiguration Controller Interfaces
December 2013
UG-01110-1.5