Altera Arria V Hard IP for PCI Express - Manual (Page 158)

8–4 Chapter 8: Register Descriptions
Configuration Space Register Content
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table 8–6 describes the Power Management Capability structure.
Table 8–7 describes the PCI Express AER Extended Capability structure.
Table 8–8 describes the PCI Express Capability Structure.
Table 8–6. Power Management Capability Structure, Rev2.1 Spec
Byte Offset 31:24 23:16 15:8 7:0
0x078 Capabilities Register Next Cap PTR Cap ID
0x07C Data
PM Control/Status
Bridge Extensions
Power Management Status & Control
Note to Table 8–6 :
(1) Refer to Table 8–39 on page 8–22 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.1.
Table 8–7. PCI Express AER Capability Structure, Rev2.1 Spec: Advanced Error Reporting Capability
Byte Offset 31:24 23:16 15:8 7:0
0x800 PCI Express Enhanced Capability Header
0x804 Uncorrectable Error Status Register
0x808 Uncorrectable Error Mask Register
0x80C Uncorrectable Error Severity Register
0x810 Correctable Error Status Register
0x814 Correctable Error Mask Register
0x818 Advanced Error Capabilities and Control Register
0x81C Header Log Register
0x82C Root Error Command
0x830 Root Error Status
0x834 Error Source Identification Register Correctable Error Source ID Register
Note to Table 8–7 :
(1) Refer to Table 8–39 on page 8–22 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.1.
Table 8–8. PCIe Capability Structure 2.1, Rev2.1 Spec (Part 1 of 2)
Byte Offset 31:16 15:8 7:0
0x080 PCI Express Capabilities Register Next Cap Pointer PCI Express Cap ID
0x084 Device Capabilities
0x088 Device Status Device Control
0x08C Link
0x090 Link Status Link Control
0x094 Slot
0x098 Slot Status Slot Control
0x09C Root Capabilities Root Control
0x0A0 Root Status
0x0A4 Device Capabilities 2