Altera Arria V Hard IP for PCI Express - Manual (Page 110)

7–12 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 7–11 shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs
for TLPs with a 3 dword header and non-qword aligned addresses. In this case,
bits[127:96] represent Data0 because address[2] is set.
Figure 7–12 shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs
for a four dword header with non-qword aligned addresses. In this example,
rx_st_empty is low because the data ends in the upper 64 bits of rx_st_data .
Figure 7–11. 128-Bit Avalon-ST rx_st_data Cycle Definition for 3-Dword Header TLP with non-Qword Aligned
Address
coreclkout
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_empty
Data0 Data 4
Header 2 Data 3
Header 1 Data 2 Data (n)
Header 0 Data 1 Data (n-1)
Figure 7–12. 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLP with non-Qword Aligned Address
coreclkout
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_empty
Header 3 Data 2
Header 2 Data 1 Data n
Header 1 Data 0 Data n-1
Header 0 Data n-2