Altera Arria V Hard IP for PCI Express - Manual (Page 221)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
16. SDC Timing Constraints
You must include component-level Synopsys Design Constraints (SDC) timing
constraints for the Arria V Hard IP for PCI Express IP Core and system-level
constraints for your complete design. The example design that Altera describes in the
Testbench and Design Example chapter includes the constraints required for the for
Arria V Hard IP for PCI Express IP Core and example design. A single file,
/ip/altera/altera_pcie/
altera_pcie_hip_ast_ed/altpcied_sv.sdc
, includes both the component-level and
system-level constraints. Example 16–1 shows altpcied_sv.sdc. This .sdc file includes
constraints for three components:
■ Arria V Hard IP for PCI Express IP Core
■ Transceiver Reconfiguration Controller IP Core
■ Transceiver PHY Reset Controller IP Core
SDC Constraints for the Hard IP for PCIe
In Example 16–1 , you should only apply the first two constraints, to derive PLL clocks
and clock uncertainty, once across all of the SDC files in your project. Differences
between Fitter timing analysis and TimeQuest timing analysis arise if these
constraints are applied more than once.
Example 16–1. SDC Timing Constraints Required for the Arria V Hard IP for PCIe and Design Example
# Constraints required for the Hard IP for PCI Express
# derive_pll_clock is used to calculate all clock derived from PCIe refclk
# the derive_pll_clocks and derive clock_uncertainty should only be applied
# once across all of the SDC files used in a project
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
##############################################################################
# PHY IP reconfig controller constraints
# Set reconfig_xcvr clock
# this line will likely need to be modified to match the actual clock pin name
# used for this clock, and also changed to have the correct period set for the actually
used clock
create_clock -period "125 MHz" -name {reconfig_xcvr_clk} {*reconfig_xcvr_clk*}
set_false_path -from
######################################################################
# HIP Soft reset controller SDC constraints
set_false_path -to [get_registers *altpcie_rs_serdes|fifo_err_sync_r[0]]
set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to [get_registers
*altpcie_rs_serdes|*]