Altera Arria V Hard IP for PCI Express - Manual (Page 12)

1–4 Chapter 1: Datasheet
Release Information
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Release Information
Table 1–2 provides information about this release of the PCI Express Compiler.
Device Family Support
Table 1–3 shows the level of support offered by the Arria V Hard IP for PCI Express.
Configurations
The Arria V Hard IP for PCI Express includes a full hard IP implementation of the
PCI Express stack including the following layers:
■ Physical (PHY)
■ Physical Media Attachment (PMA)
■ Physical Coding Sublayer (PCS)
■ Media Access Control (MAC)
■ Data Link Layer (DL)
■ Transaction Layer (TL)
Optimized for Altera devices, the Arria V Hard IP for PCI Express supports all
memory, I/O, configuration, and message transactions. It has a highly optimized
Application Layer interface to achieve maximum effective throughput. You can
customize the Hard IP to meet your design requirements using either the
MegaWizard
Plug-In Manager or the Qsys design flow.
Table 1–3. PCI Express Compiler Release Information
Item Description
Version 13.1
Release Date December 2013
Ordering Codes No ordering code is required
Product IDs There are no encrypted files for the Arria V Hard IP for PCI
Express. The Product ID and Vendor ID are not required
because this IP core does not require a license.
Vendor ID
Table 1–4. Device Family Support
Device Family Support
Arria V
Final. The IP core is verified with final timing models. The
IP core meets all functional and timing requirements for
the device family and can be used in production designs.
Other device families
Refer to the following user guides for other device families:
■ IP Compiler for PCI Express User Guide
■ Arria V GZ Hard IP for PCI Express User Guide’
■ Cyclone V Hard IP for PCI Express User Guide
■ Stratix V Hard IP for PCI Express User Guide
■ Arria 10 Hard IP for PCI Express User Guide