Altera Arria V Hard IP for PCI Express User Manual
Page 202
11–8
Chapter 11: Interrupts
Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
■
An MSI-X table to store the MSI-X table entries. The PCIe Root Port sets up this
table.
Refer to
R**Interrupts for Endpoints ###if_irqs#
for the definitions of MSI, MSI-X and
INTx buses.
1. For more information about implementing MSI or MSI-X interrupts, refer to the
Figure 11–6. Block Diagram for Custom Interrupt Handler
M
S
MSI/MSI-X IRQ
S
MSI-X Table Entries
Qsys
Interconnects
S
M
PCIe-Avalon-MM
Bridge
Hard
IP for
PCIe
PCIe
Root
Port
MSI or
MXI-X
Req
IRQ Cntl
& Status
Table &
PBA
RXM
Exported MSI/MSI-X/INTX
IntxReq_i
Custom
Interrupt Handler
Qsys System
MSI-X PBA
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)