Altera Arria V Hard IP for PCI Express - Manual (Page 195)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
11. Interrupts
This chapter describes interrupts for the following configurations:
■ Interrupts for Endpoints Using the Avalon-ST Application Interface
■ Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
■ Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
Refer to “Interrupts for Endpoints” on page 7–28 and “Interrupts for Root Ports” on
page 7–28 for descriptions of the interrupt signals.
Interrupts for Endpoints Using the Avalon-ST Application Interface
The Arria V Hard IP for PCI Express provides support for PCI Express MSI, MSI-X,
and legacy interrupts when configured in Endpoint mode. The MSI, MSI-X, and
legacy interrupts are mutually exclusive. After power up, the Hard IP block starts in
INTX mode, after which time software decides whether to switch to MSI mode by
programming the
msi_enable bit of the MSI message control register (bit[16] of
0x050) to 1 or to MSI-X mode if you turn on Implement MSI-X under the PCI
Express/PCI Capabilities
tab using the parameter editor. If you turn on the
Implement MSI-X option, you should implement the MSI-X table structures at the
memory space pointed to by the BARs.
f Refer to section 6.1 of PCI Express 2.1 Base Specification for a general description of PCI
Express interrupt support for Endpoints.
MSI Interrupts
MSI interrupts are signaled on the PCI Express link using a single dword memory
write TLPs generated internally by the Arria V Hard IP for PCI Express. The
app_msi_req input port controls MSI interrupt generation. When the input port
asserts app_msi_req , it causes a MSI posted write TLP to be generated based on the
MSI configuration register values and the app_msi_tc and app_msi_num input ports.
Software uses configuration requests to program the MSI registers. To enable MSI
interrupts, software must first set the
MSI enable bit ( Table 7–14 on page 7–38 ) and
then disable legacy interrupts by setting the Interrupt Disable which is bit 10 of the
Command register ( Table 8–2 on page 8–2 ).
December 2013
UG-01110-1.5