Altera Arria V Hard IP for PCI Express User Manual
Page 163
Chapter 8: Register Descriptions
8–9
Altera-Defined Vendor Specific Extended Capability (VSEC)
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
Table 8–19
defines the fields of the
Uncorrectable Internal Error Status
register.
This register reports the status of the internally checked errors that are uncorrectable.
When specific errors are enabled by the
Uncorrectable Internal Error Mask
register, they are handled as Uncorrectable Internal Errors as defined in the
This register is for debug only. It should only be used to
observe behavior, not to drive logic custom logic.
Table 8–20
defines the
Uncorrectable Internal Error Mask
register. This register
controls which errors are forwarded as internal uncorrectable errors. With the
exception of the configuration error detected in CvP mode, all of the errors are severe
and may place the device or PCIe link in an inconsistent state. The configuration error
detected in CvP mode may be correctable depending on the design of the
programming software.
Table 8–19. Uncorrectable Internal Error Status Register
Bits
Register Description
Access
[31:12]
Reserved.
RO
[11]
When set, indicates an RX buffer overflow condition in a posted request or Completion
RW1CS
[10]
Reserved.
RO
[9]
When set, indicates a parity error was detected on the Configuration Space to TX bus interface
RW1CS
[8]
When set, indicates a parity error was detected on the TX to Configuration Space bus interface
RW1CS
[7]
When set, indicates a parity error was detected in a TX TLP and the TLP is not sent.
RW1CS
[6]
When set, indicates that the Application Layer has detected an uncorrectable internal error.
RW1CS
[5]
When set, indicates a configuration error has been detected in CvP mode which is reported as
uncorrectable. This bit is set whenever a
CVP_CONFIG_ERROR
rises while in
CVP_MODE
.
RW1CS
[4]
When set, indicates a parity error was detected by the TX Data Link Layer.
RW1CS
[3]
When set, indicates a parity error has been detected on the RX to Configuration Space bus
interface.
RW1CS
[2]
When set, indicates a parity error was detected at input to the RX Buffer.
RW1CS
[1]
When set, indicates a retry buffer uncorrectable ECC error.
RW1CS
[0]
When set, indicates a RX buffer uncorrectable ECC error.
RW1CS
Table 8–20. Uncorrectable Internal Error Mask Register (Part 1 of 2)
Bits
Register Description
Reset Value
Access
[31:12]
Reserved.
1b’0
RO
[11]
Mask for RX buffer posted and completion overflow error.
1b’1
RWS
[10]
Reserved
1b’0
RO
[9]
Mask for parity error detected on Configuration Space to TX bus interface.
1b’1
RWS
[8]
Mask for parity error detected on the TX to Configuration Space bus interface.
1b’1
RWS
[7]
Mask for parity error detected at TX Transaction Layer error.
1b’1
RWS
[6]
Reserved
1b’0
RO
[5]
Mask for configuration errors detected in CvP mode.
1b’0
RWS
[4]
Mask for data parity errors detected during TX Data Link LCRC generation.
1b’1
RWS
[3]
Mask for data parity errors detected on the RX to Configuration Space Bus
interface.
1b’1
RWS