Altera Arria V Hard IP for PCI Express - Manual (Page 280)

A–2 Chapter :
TLP Packet Format without Data Payload
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table A–5. Configuration Read Request Root Port (Type 1)
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 R 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 TD EP 0 0 AT 0 0 0 0 0 0 0 0 0 1
Byte 4 Requester ID Tag 0 0 0 0 First BE
Byte 8 Bus Number Device No Func 0 0 0 0 Ext Reg Register No 0 0
Byte 12 Reserved
Table A–6. I/O Read Request
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TD EP 0 0 AT 0 0 0 0 0 0 0 0 0 1
Byte 4 Requester ID Tag 0 0 0 0 First BE
Byte 8 Address[31:2] 0 0
Byte 12 Reserved
Table A–7. Message without Data
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 1 1 0
r
2 r
1 r
0
0 TC 0 0 0 0 TD EP 0 0 AT 0 0 0 0 0 0 0 0 0 0
Byte 4 Requester ID Tag Message Code
Byte 8 Vendor defined or all zeros
Byte 12 Vendor defined or all zeros
Notes to Table A–7 :
(1) Not supported in Avalon-MM.
Table A–8. Completion without Data
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 0 0 1 0 1 0 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Completer ID Status B Byte Count
Byte 8 Requester ID Tag 0 Lower Address
Byte 12 Reserved
Table A–9. Completion Locked without Data
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 0 0 1 0 1 1 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Completer ID Status B Byte Count
Byte 8 Requester ID Tag 0 Lower Address
Byte 12 Reserved