Altera Arria V Hard IP for PCI Express - Manual (Page 34)

2–18 Chapter 2: Getting Started with the Arria Hard IP for PCI Express
Modifying the Example Design
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Modifying the Example Design
To use this example design as the basis of your own design, replace the Chaining
DMA Example shown in
Figure 2–6 with your own Application Layer design. Then
modify the Root Port BFM driver to generate the transactions needed to test your
Application Layer.
.
Figure 2–6. Testbench for PCI Express
PCB
Avalon-MM slave
Reset
Stratix V Hard IP for PCI Express
Stratix V FPGA
PCB
Transaction Layer
Data Link Layer
PHY MAC Layer
x8 PCIe Link
(Physical Layer)
Lane 7
(Unused)
(Unused)
Lane 6
Lane 5
TX PLL
PHY IP Core for PCI Express
Lane 2
Lane 3
Lane 4
Lane 1
Lane 0
TX PLL
Transceiver Bank
Transceiver Bank
S
Reconfig
to and from
Transceiver
to and from
Embedded
Controller
(Avalon-MM
slave interface)
Transceiver
Reconfiguration
Controller
Root
Port
BFM
npor
Reset
APPS DUT
Chaining DMA
(User Application)