Device, Device –4 – Altera Arria V Hard IP for PCI Express User Manual
Page 68
5–4
Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express
PCI Express/PCI Capabilities
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
Device
Table 5–4
describes the device parameters.
1
Some of these parameters are stored in the
Common Configuration Space Header
Text in
green
are links to these parameters stored in the
Table 5–4. Capabilities Registers for Function
Parameter
Possible
Values
Default
Value
Description
Device Capabilities
Maximum
payload size
128 bytes
256 bytes
128 bytes
Specifies the maximum payload size supported. This
parameter sets the read-only value of the max payload size
supported field of the Device Capabilities register (0x084[2:0])
and optimizes the IP core for this size payload. You should
optimize this setting based on your typical expected
transaction sizes.
Completion
timeout range
ABCD
BCD
ABC
AB
B
A
None
ABCD
Indicates device function support for the optional completion
timeout programmability mechanism. This mechanism allows
system software to modify the completion timeout value. This
field is applicable only to Root Ports and Endpoints that issue
requests on their own behalf. Completion timeouts are
specified and enabled in the Device Control 2 register (0x0A8)
of the PCI Express Capability Structure Version 2.0 described
in
. For all other functions this field is
reserved and must be hardwired to 0x0000b. Four time value
ranges are defined:
■
Range A: 50 µs to 10 ms
■
Range B: 10 ms to 250 ms
■
Range C: 250 ms to 4 s
■
Range D: 4 s to 64 s
Bits are set to show timeout value ranges supported. 0x0000b
completion timeout programming is not supported and the
function must implement a timeout value in the range 50 s to
50 ms.
The following encodings are used to specify the range:
■
0001 Range A
■
0010 Range B
■
0011 Ranges A and B
■
0110 Ranges B and C
■
0111 Ranges A, B, and C
■
1110 Ranges B, C and D
■
1111 Ranges A, B, C, and D