Altera Arria V Hard IP for PCI Express - Manual (Page 218)

15–2 Chapter 15: Transceiver PHY IP Reconfiguration
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
When you instantiate the Transceiver Reconfiguration Controller, you must specify 5
for the Number of reconfiguration interfaces as illustrates.
The Transceiver Reconfiguration Controller includes an Optional interface grouping
parameter. Arria V devices include six channels in a transceiver bank. For a ×4
variant, no special interface grouping is required because all 4 lanes and the TX PLL
fit in one bank.
1 Although you must initially create a separate logical reconfiguration interface for each
lane and TX PLL in your design, when the Quartus II software compiles your design,
it reduces original number of logical interfaces by merging them. Allowing the
Quartus II software to merge reconfiguration interfaces gives the Fitter more
flexibility in placing transceiver channels.
1 You cannot use SignalTap TM to observe the reconfiguration interfaces.
Figure 15–2.