Altera Arria V Hard IP for PCI Express User Manual
Page 38

3–4
Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express
Customizing the Arria V Hard IP for PCI Express IP Core
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
4. Under the PCI Express and PCI Capabilities heading, specify the settings in
Revision ID
0x00000001
0x00000001
Class Code
0x00000000
0x00FF0000
Subsystem Vendor ID
0x00000000
0x00001172
Subsystem Device ID
0x00000000
0x0000E001
Table 3–5. PCI Express and PCI Capabilities
Parameter
Value
Device
Maximum payload size
128 Bytes
Completion timeout range
ABCD
Implement completion timeout disable
Turn on this option
Error Reporting
Advanced error reporting (AER)
Turn off this option
ECRC checking
Turn off this option
ECRC generation
Turn off this option
Link
Link port number
1
Slot clock configuration
Turn on this option
MSI
Number of MSI messages requested
4
MSI-X
Implement MSI-X
Turn this option off
Power Management
Endpoint L0s acceptable latency
Maximum of 64 ns
Endpoint L1 acceptable latency
Maximum of 1 us
Table 3–4. Device Identification Registers (Part 2 of 2)
Parameter
Value
Altera Value
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)