Altera Arria V Hard IP for PCI Express - Manual (Page 113)

Chapter 7: IP Core Interfaces 7–15
Arria V Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Avalon-ST TX Interface
Table 7–4 describes the signals that comprise the Avalon-ST TX Datapath. The TX data
signal can be 64 or 128 bits.
Table 7–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 1 of 4)
Signal Width Dir
Avalon-ST
Type
Description
tx_st_data
64,
128
I data
Data for transmission. Transmit data bus. Refer to
Figure 7–17 through Figure 7–21 for the mapping of TLP
packets to tx_st_data and examples of the timing of the
64-bit interface. Refer to Figure 7–22 through Figure 7–27
for the mapping of TLP packets to tx_st_data and
examples of the timing of the 128-bit interface.
The Application Layer must provide a properly formatted
TLP on the TX interface. The mapping of message TLPs is
the same as the mapping of Transaction Layer TLPs with 4
dword headers. The number of data cycles must be correct
for the length and address fields in the header. Issuing a
packet with an incorrect number of data cycles results in
the TX interface hanging and unable to accept further
requests.
tx_st_sop 1 I
start of
packet
Indicates first cycle of a TLP when asserted in the same
cycle with
tx_st_valid .
tx_st_eop 1 I
end of
packet
Indicates last cycle of a TLP when asserted in the same
cycle with
tx_st_valid .
tx_st_ready (1) 1 O ready
Indicates that the Transaction Layer is ready to accept data
for transmission. The core deasserts this signal to throttle
the data stream.
tx_st_ready may be asserted during
reset. The Application Layer should wait at least 2 clock
cycles after the reset is released before issuing packets on
the Avalon-ST TX interface. The
reset_status signal can
also be used to monitor when the Hard IP has come out of
reset.
If tx_st_ready is asserted by the Transaction Layer on
cycle , then readyLatency> is a ready cycle,
during which the Application Layer may assert valid and
transfer data.
When tx_st_ready , tx_st_valid and tx_st_data are
registered (the typical case), Altera recommends a
readyLatency of 2 cycles to facilitate timing closure;
however, a readyLatency of 1 cycle is possible.