Altera Arria V Hard IP for PCI Express User Manual
Page 152

7–54
Chapter 7: IP Core Interfaces
Physical Layer Interface Signals
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
ltssmstate0[4:0]
LTSSM state: The LTSSM state machine encoding defines the following
states:
■
00000: detect.quiet
■
00001: detect.active
■
00010: polling.active
■
00011: polling.compliance
■
00100: polling.configuration
■
00101: polling.speed
■
00110: config.linkwidthstart
■
00111: config.linkaccept
■
01000: config.lanenumaccept
■
01001: config.lanenumwait
■
01010: config.complete
■
01011: config.idle
■
01100: recovery.rcvlock
■
01101: recovery.rcvconfig
■
01110: recovery.idle
■
01111: L0
■
10000: disable
■
10001: loopback.entry
■
10010: loopback.active
■
10011: loopback.exit
■
10100: hot.reset
■
10101: LOs
■
11001: L2.transmit.wake
■
11010: speed.recovery
O
sim_pipe_rate[1:0]
O
Specifies the lane rate. The 2-bit encodings have the following
meanings:
■
2’b00: Gen1 rate (2.5 Gbps)
■
2’b01: Gen2 rate (5.0 Gbps)
■
2’b1X: Reserved.
sim_pipe_pclk_in
I
This clock is used for PIPE simulation only, and is derived from the
refclk
. It is the PIPE interface clock used for PIPE mode simulation.
txswing0
O
Specifies the following TX voltage swing levels. A value of 0 specifies full
swing. A value of 1 specifies half swing.
Table 7–26. PIPE Interface Signals (Part 3 of 4)
Signal I/O
Description