Register descriptions, Configuration space register content, Chapter 8. register descriptions – Altera Arria V Hard IP for PCI Express User Manual
Page 155: Configuration space register content –1, Common configuration space, Header, Chapter, In the, Common configuration space header, Configuration space register
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
8. Register Descriptions
This section describes registers that you can access the PCI Express Configuration
Space. It includes the following sections:
■
Configuration Space Register Content
■
Correspondence between Configuration Space Registers and the PCIe Spec 2.1
Configuration Space Register Content
shows the PCI Compatible Configuration Space address map. The following
tables provide more details.
1
To facilitate finding additional information about these PCI and PCI Express registers,
the following tables provide the name of the corresponding section in the
f
For comprehensive information about these registers, refer to Chapter 7 of the
Table 8–1. Common Configuration Space Header
Byte Offset
Register Set
0x000:0x03C
PCI Type 0 Configuration Space Header (Refer to
for details) or PCI Type 1 Configuration
Space Header (Refer to
for details.)
0x040:0x04C
Reserved.
0x050:0x05C
MSI Capability Structure (Refer to
for details.)
0x060:0x064
Reserved
0x068:0x070
MSI-X Capability Structure (Refer to
for details.)
0x071:0x074
Reserved
0x078:0x07C
Power Management Capability Structure (Refer to
for details.)
0x080:0x0BC
PCI Express Capability Structure (Refer to
for details.)
0x0C0:0x0C4
Reserved
0x0C8-0x7FC
Reserved
0x800:0x834
Advanced error reporting (AER)
(optional)
0x838:0xFFF
Reserved
0x100:0x16C
Virtual Channel Capability Structure for Function 0, Vendor Specific Extended Capability for Functions
1–7
December 2013
UG-01110-1.5