Altera Arria V Hard IP for PCI Express - Manual (Page 69)

Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express 5–5
PCI Express/PCI Capabilities
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Error Reporting
Table 5–5 describes the Advanced Error Reporting (AER) and ECRC parameters.
Link
Table 5–6 describes the Link Capabilities parameters.
Completion
timeout range
(continued)
All other values are reserved. Altera recommends that the
completion timeout mechanism expire in no less than 10 ms.
Implement
completion
timeout
disable
0x0A8
On/Off On
For PCI Express version 2.0 and higher Endpoints, this option
must be On. The timeout range is selectable. When On, the
core supports the completion timeout disable mechanism via
the PCI Express
Device Control Register 2 . The
Application Layer logic must implement the actual completion
timeout mechanism for the required ranges.
Table 5–4. Capabilities Registers for Function (Part 2 of 2)
Parameter
Possible
Values
Default
Value
Description
Table 5–5. Error Reporting 0x800 – 0x834
Parameter Value
Default
Value
Description
Advanced error
reporting (AER)
On/Off Off When On, enables the AER capability.
ECRC checking On/Off Off
When On, enables ECRC checking. Sets the read-only value of the
ECRC check capable bit in the
Advanced Error Capabilities
and Control Register . This parameter requires you to enable the
AER capability.
ECRC generation On/Off Off
When On, enables ECRC generation capability. Sets the read-only
value of the ECRC generation capable bit in the
Advanced Error
Capabilities and Control Register . This parameter requires
you to enable the AER capability.
Note to Table 5–5 :
(1) Throughout The Arria V Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the
PCI Express Base Specification Revision 2.1 or 3.0 . A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.
Table 5–6. Link Capabilities 0x090
Parameter Value Description
Link port number
0x01
(Default
value)
Sets the read-only value of the port number field in the Link Capabilities
register. This is an 8-bit field which you can specify.
Slot clock
configuration
On/Off
When On, indicates that the Endpoint or Root Port uses the same physical reference
clock that the system provides on the connector. When Off, the IP core uses an
independent clock regardless of the presence of a reference clock on the connector.