Altera Arria V Hard IP for PCI Express - Manual (Page 111)

Chapter 7: IP Core Interfaces 7–13
Arria V Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Figure 7–13 shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs
for a four dword header with qword aligned addresses.
Figure 7–14 illustrates the timing of the RX interface when the Application Layer
backpressures the Hard IP by deasserting rx_st_ready . The rx_st_valid signal must
deassert within three cycles after rx_st_ready is deasserted. In this example,
rx_st_valid is deasserted in the next cycle.
Figure 7–13. 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLP with Qword Aligned Address
coreclkout
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_empty
Header3 Data3 Data n
Header 2 Data 2 Data n-1
Header 1 Data 1 Data n-2
Header 0 Data 0 Data n-3
Figure 7–14. 128-Bit Application Layer Backpressures Hard IP Transaction Layer for RX Transactions
coreclkout
rx_st_data[127:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
4562 . . . c19a . . . 0217b . . . 134c . . . 8945 . . . 3458ce. . . 2457ce. . . 000a7896c000bc34. .