Avalon to pcie address translation settings, Avalon to pcie address translation settings –10 – Altera Arria V Hard IP for PCI Express User Manual
Page 74
5–10
Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express
Avalon to PCIe Address Translation Settings
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
Avalon to PCIe Address Translation Settings
Table 5–11
lists the Avalon-MM PCI Express address translation parameter registers.
Table 5–11. Avalon Memory-Mapped System Settings
Parameter
Value
Description
Number of address
pages
1,2,4,8,16,32,64,
128,256,512
Specifies the number of pages required to translate Avalon-MM addresses
to PCI Express addresses before a request packet is sent to the Transaction
Layer. Each of the 512 possible entries corresponds to a base address of
the PCI Express memory segment of a specific size.
Size of address
pages
4 KByte –4 GBytes
Specifies the size of each memory segment. Each memory segment must
be the same size. Refer to
“Avalon-MM-to-PCI Express Address Translation
for more information about address translation.
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- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
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- Device-Specific Power Delivery Network (28 pages)
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- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
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