Altera Arria V Hard IP for PCI Express - Manual (Page 93)

Chapter 6: IP Core Architecture 6–19
Avalon-MM Bridge TLPs
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Figure 6–8 illustrates this Qsys system. ( Figure 6–8 uses a filter to hide the Conduit
interfaces that are not relevant in this discussion.)
Figure 6–9 illustrates the address map for this system.
The auto-assigned base addresses result in the following three large BARs:
■ BAR0 is 28 bits. This is the optimal size because it addresses the
Offchip_Data_Mem
which requires 28 address bits.
■ BAR2 is 29 bits. BAR2 addresses the Quick_Data_Mem which is 4 KBytes;. It
should only require 12 address bits; however, it is consuming 512 MBytes of
address space.
■ BAR4 is also 29 bits. BAR4 address PCIe Cra which is 16 KBytes. It should only
require 14 address bits; however, it is also consuming 512 MBytes of address space.
Figure 6–8. Qsys System for PCI Express with Poor Address Space Utilization
Figure 6–9. Poor Address Map