Altera Arria V Hard IP for PCI Express - Manual (Page 22)

2–6 Chapter 2: Getting Started with the Arria Hard IP for PCI Express
Customizing the Endpoint in the MegaWizard Plug-In Manager Design Flow
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
19. On the Func 0 Device tab, under PCI Express/PCI Capabilities for Func 0 turn
Function Level Reset (FLR) Off .
20. Table 2–7 lists settings for the Func0 Link tab.
21. On the Func0 MSI tab, for Number of MSI messages requested, select 4.
22. On the Func0 MSI-X tab, turn Implement MSI-X off.
23. On the Func0 Legacy Interrupt tab, select INTA.
24. the following tablethe following tablethe following tablethe following tablethe
following tablethe following tableClick Finish. The Generation dialog box
appears.
25. Turn on Generate Example Design to generate the Endpoint, testbench, and
supporting files.
26. Click Exit.
27. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the project.
The .qip is a file generated by the parameter editor contains all of the necessary
assignments and information required to process the IP core in the Quartus II
compiler. Generally, a single .qip file is generated for each IP core.
Understanding the Files Generated
The following table provides an overview of directories and files generated.
Follow these steps to generate the chaining DMA testbench from the Qsys system
design example.
1. On the Quartus II File menu, click Open.
2. Navigate to the Qsys system in the altera_pcie__hip_ast subdirectory.
Subsystem Vendor ID 0x00000000 0x00001172
Subsystem Device ID 0x00000000 0x0000E001
Table 2–7. Link Capabilities
Parameter Value
Data link layer active reporting Off
Surprise down reporting Off
Table 2–6. Device ID Registers for Func0
Table 2–8. Qsys Generation Output Files
Directory Description
// Includes the files for synthesis
<working_dir>/_sim/
altera_pcie__hip_ast
Includes the simulation files.
<working_dir>/_example_design/
altera_pcie__hip_ast
Includes a Qsys testbench that connects the Endpoint to a chaining
DMA engine, Transceiver Reconfiguration Controller, and driver for the
Transceiver Reconfiguration Controller.