Altera Arria V Hard IP for PCI Express User Manual
Page 182
9–2
Chapter 9: Reset and Clocks
Reset
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
Figure 9–1. Reset Controller
Example Design
altpcie_dev_hip_ast_hwtcl.v
altpcied_
Transceiver Hard
Reset Logic/Soft Reset
Controller
Configuration Space
Sticky Registers
Datapath State
Machines of
Hard IP Core
SERDES
Configuration Space
Non-Sticky Registers
reset_status
pld_clk
pin_perstn
npor
refclk
srst
crst
l2_exit
hotrst_exit
dlup_exit
pld_clk_inuse
Hard IP for PCI Express
fixed_clk
(100 or 125 MHz)
reconfig_xcvr_clk
mgmt_rst_reset
reconfig_busy
Transceiver
Reconfiguration
Controller
reconfig_xcvr_clk
reconfig_busy
reconfig_xcvr_rst
pcie_reconfig_
driver_0
altpcie_
altpcie_rs_serdes.v
coreclkout_hip
coreclkout_hip
top.v
tx_digitalrst
rx_analogrst
rx_digitalrst
rx_freqlock
rx_signaldetect
rx_pll_locked
pll_locked
tx_cal_busy
rx_cal_busy
Chaining
DMA
(APPs)
reconfig_clk
mgmt_rst_reset
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)