Altera Arria V Hard IP for PCI Express - Manual (Page 77)

Chapter 6: IP Core Architecture 6–3
Key Interfaces
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Key Interfaces
If you select the Arria V Hard IP for PCI Express, your design includes an Avalon-ST
interface to the Application Layer. If you select the Avalon-MM Arria V Hard IP for
PCI Express, your design includes an Avalon-MM interface to the Application Layer.
The following sections introduce the interfaces shown in
Figure 6–2 .
.
Avalon-ST Interface
An Avalon-ST interface connects the Application Layer and the Transaction Layer.
This is a point-to-point, streaming interface designed for high throughput
applications. The Avalon-ST interface includes the RX and TX datapaths.
f For more information about the Avalon-ST interface, including timing diagrams, refer
to the
Avalon Interface Specifications .
RX Datapath
The RX datapath transports data from the Transaction Layer to the Application
Layer’s Avalon-ST interface. Masking of non-posted requests is partially supported.
Refer to the description of the
rx_st_mask signal for further information about
masking. For more information about the RX datapath, refer to “Avalon-ST RX
Interface” on page 7–6 .
TX Datapath
The TX datapath transports data from the Application Layer's Avalon-ST interface to
the Transaction Layer. The Hard IP provides credit information to the Application
Layer for posted headers, posted data, non-posted headers, non-posted data,
completion headers and completion data.
The Application Layer may track credits consumed and use the credit limit
information to calculate the number of credits available. However, to enforce the PCI
Express Flow Control (FC) protocol, the Hard IP also checks the available credits
before sending a request to the link, and if the Application Layer violates the available
credits for a TLP it transmits, the Hard IP blocks that TLP and all future TLPs until
Figure 6–2.
PMA PCS
Hard IP for PCI Express
Altera FPGA
Avalon-ST
Interrupts
Clocks and Reset
LMI
PIPE Interface
Transceiver
Reconfiguration
PHY IP Core for
PCI Express (PIPE)