Altera Arria V Hard IP for PCI Express - Manual (Page 210)

13–4 Chapter 13: Flow Control
Throughput of Non-Posted Reads
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Nevertheless, maintaining maximum throughput of completion data packets is
important. Endpoints must offer an infinite number of completion credits. Endpoints
must buffer this data in the RX buffer until the Application Layer can process it.
Because the Endpoint is no longer managing the RX buffer through the flow control
mechanism, the Application Layer must manage the RX buffer by the rate at which it
issues read requests.
To determine the appropriate settings for the amount of space to reserve for
completions in the RX buffer, you must make an assumption about the length of time
until read completions are returned. This assumption can be estimated in terms of an
additional delay, beyond the FC Update Loop Delay, as discussed in the section
“Throughput of Posted Writes” on page 13–1 . The paths for the read requests and the
completions are not exactly the same as those for the posted writes and FC Updates in
the PCI Express logic. However, the delay differences are probably small compared
with the inaccuracy in the estimate of the external read to completion delays.
With multiple completions, the number of available credits for completion headers
must be larger than the completion data space divided by the maximum packet size.
Instead, the credit space for headers must be the completion data space (in bytes)
divided by 64, because this is the smallest possible read completion boundary. Setting
the RX Buffer space allocation – Desired performance for received completions to
High
under the System Settings heading when specifying parameter settings
configures the RX buffer with enough space to meet this requirement. You can adjust
this setting up or down from the High setting to tailor the RX buffer size to your
delays and required performance.
You can also control the maximum amount of outstanding read request data. This
amount is limited by the number of header tag values that can be issued by the
Application Layer and by the maximum read request size that can be issued. The
number of header tag values that can be in use is also limited by the Arria V Hard IP
for PCI Express. You can specify 32 or 64 tags though configuration software to
restrict the Application Layer to use only 32 tags. In commercial PC systems, 32 tags
are usually sufficient to maintain optimal read throughput.